Senior Staff Engineer Verification
Core
Develop and own System Verilog/UVM-based verification environments for ASIC/SoC DSP and arithmetic datapath blocks, integrating C/MATLAB reference models for RTL correlation.
Role type
Senior IC verification engineer (ASIC/SoC)
Builds
Verified RTL designs for power systems and IoT semiconductor solutions
Domain
Semiconductor / Hardware Verification
Deliverable
production ML models
Required skills
SystemVerilog, UVM, Functional Coverage, Code Coverage, RAL, Fixed-point arithmetic, MATLAB/Simulink, Constrained-random verification, Regression management, Root-cause analysis
Preferred skills
DSP filter behavior analysis, Model-based verification, Silicon bring-up support
Technologies
SystemVerilog, UVM, MATLAB, Simulink, Fixed-Point Designer
Responsibilities
Develop verification environments including scoreboards, sequences, and regressions; Verify DSP and arithmetic datapath blocks; Integrate C/MATLAB reference models; Perform regression management and failure triage; Support silicon bring-up and resolve functional issues.
Seniority
Senior, hands-on IC
