Staff IC Verification Engineer
Core
Developing verification environments and test cases for state-of-the-art AI and storage SoC and embedded IP subsystems.
Role type
Staff IC Verification Engineer
Builds
Verification environments, testbenches, and coverage models for AI and storage chips
Domain
Semiconductor / SoC Design / Hardware Verification
Required skills
SystemVerilog, UVM, constrained random verification, HDL simulation debugging, C++, OOP, coverage analysis, assertion development
Preferred skills
Matrix organization communication, independent problem solving, leadership
Technologies
System Verilog, UVM, Verilog, VHDL, C++, Java, HDL simulators
Responsibilities
Develop verification environments using System Verilog and UVM; Design verification classes (sequences, agents, scoreboards); Implement coverage and assertions; Develop random and directed test cases; Analyze and debug simulation failures and coverage results.
Seniority
Staff, hands-on IC
