R&D Engineer IC Design
Core
Design and verification of DFT (Design for Test) architectures, test insertion, pattern generation, and post-silicon debug for Broadcom ASIC SoC designs.
Role type
Senior IC Design Engineer (DFT)
Builds
ASIC SoC designs with integrated DFT for testability and yield improvement
Domain
Semiconductor / ASIC Design
Required skills
DFT architecture, ATPG, MBIST, JTAG, DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug, Perl scripting, Shell scripting
Preferred skills
Siemens-Mentor Graphics DFT tools (TestKompress, Fastscan), cross-geography team collaboration
Responsibilities
Work on DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement, Collaborate with Physical Design & STA team for DFT mode timing closure, Interact with external customers
Seniority
Senior, hands-on IC with supervision responsibilities
