Trainee Engineer
Core
Trainee Engineer developing simulation and emulation testbenches for Graphics/Security IP to ensure functional correctness of complex digital architectures.
Role type
Trainee Digital Design Verification Engineer
Builds
Simulation and emulation testbenches for Graphics and Security IP
Domain
Semiconductor / Digital Design Verification
Required skills
SystemVerilog, UVM, Digital Logic Design, Computer Architecture, Python/Perl/Bash scripting
Preferred skills
ASIC/FPGA internship, Graphics IP knowledge, Hardware emulation platforms, EDA tools (Synopsys/Cadence)
Technologies
SystemVerilog, UVM, Python, Perl, Bash, VCS, Questa, Xcelium, Palladium, Zebu, Veloce
Responsibilities
Develop block-level and chip-level simulation testbenches, Write scalable verification components (drivers, monitors, scoreboards), Collaborate on emulation testbenches for pre-silicon validation, Map out verification plans for Graphics IPs, Run regressions and debug hardware failures
Seniority
Junior, Trainee (Graduation within last 12 months)
