Staff Engineer, DFT
Core
Designing and implementing low-power Design for Test (DFT) architectures and infrastructure for ultra-low power System-on-Chip (SoC) devices based on subthreshold operation.
Role type
Staff Engineer, DFT
Builds
Low-power DFT architecture and infrastructure for ultra-low power SoCs
Domain
Semiconductor / Ultra-low power IC design
Required skills
DFT implementation, scan insertion, boundary scan, MBIST, ATPG, hierarchical DFT architecture, low-power DFT, test coverage analysis, timing concepts, RTL design, EDA tools
Preferred skills
Tcl scripting, gate level simulation (GLS)
Responsibilities
Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools. Develop and implement low-power DFT architecture and infrastructure. Generate structural test vectors, analyse, and improve coverage, test time and test cost. Perform pre/post-layout scan and MBIST simulations. Work with designers on STA, physical, power and logical issues related to DFT. Work with test engineers to bring up test vectors on silicon.
Seniority
Staff, hands-on IC
