Staff Design Engineer
Core
Designing and integrating complex IP and compute subsystems for Edge, Physical, and Cloud AI systems using RTL and microarchitecture.
Role type
Staff Subsystem Design Engineer (SoC/RTL)
Builds
Highly integrated and optimized SoC IPs and subsystem solutions for next-generation AI systems.
Domain
Semiconductor / Computer Architecture / AI Hardware
Deliverable
production ML models
Required skills
Digital RTL design (SystemVerilog/Verilog), Microarchitecture development, IP integration, Static design checks (Lint, CDC, RDC), Synthesis and timing analysis, Low-power design (UPF, power gating), On-chip protocols (AMBA AXI, APB), Computer architecture knowledge, EDA tools, AI coding assistants
Preferred skills
Arm-based designs, Advanced low-power RTL, SystemVerilog Assertions (SVA), Formal verification, UVM, Functional Safety, C/C++ programming
Technologies
SystemVerilog, Verilog, UPF, AMBA AXI, APB, Lint, CDC, RDC, EDA tools, GitHub Copilot, Codex
Responsibilities
Analyze architectural specifications and collaborate with architects to refine solutions, Develop subsystem and IP microarchitecture specifications, Design new IP and integrate existing Arm/third-party IP, Perform static design checks and drive design quality, Navigate PPA trade-offs and articulate design rationale, Collaborate with verification and implementation teams, Improve design methodologies and flows, Provide technical guidance and design reviews
Seniority
Staff, hands-on IC with mentorship
