Director, Logical Design
Core
Lead the RTL design, development, and integration of critical subsystems for next-generation AI acceleration platforms (SoCs).
Role type
Director, SoC Design (Engineering Leader)
Builds
High-performance AI acceleration SoCs
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
ASIC/SoC design, RTL development (Verilog/SystemVerilog), microarchitecture, SoC integration, synthesis, static timing analysis, CDC/RDC, low-power design, physical implementation, team leadership, technical risk management
Preferred skills
AI accelerator SoC development, advanced process technologies, physically aware RTL, DFT, multi-die/chiplet architectures, high-speed interfaces (PCIe, DDR, Ethernet), silicon bring-up, design automation
Technologies
Verilog, SystemVerilog, SoC interconnect protocols, clock/reset architectures, synthesis tools, static timing analysis tools, DFT methodologies
Responsibilities
Provide technical leadership for microarchitecture and SoC integration; Lead engineering execution and delivery of complex SoC designs; Drive design quality and implementation readiness; Collaborate with architecture, verification, DFT, and physical design teams; Identify and manage technical risks and cross-functional dependencies; Build and develop high-performing engineering teams; Drive continuous improvement in design methodologies and processes
Seniority
Director, hands-on IC with people leadership
