Physical Design Team Lead
Core
Lead physical design teams to take complex, high-speed mixed-signal and digital SoCs from RTL handoff through tapeout for rack-scale AI infrastructure.
Role type
Principal Physical Design Engineer and Team Lead
Builds
Custom connectivity solutions and standards-based silicon for hyperscalers and ecosystem partners
Domain
Semiconductor / AI Infrastructure / High-Speed Connectivity
Required skills
Physical design of complex SoCs/ASICs, Floorplanning, Placement, Clock tree synthesis, Routing, Timing closure, Power integrity, Signal integrity, Physical verification (STA, IR/EM, DRC, LVS), ECO management, Team leadership, Project management, Foundry/EDA/IP collaboration
Preferred skills
High-speed interface design (PCIe, Ethernet, SerDes), Scripting (Tcl, Python, Perl), Hierarchical design, Low-power methodologies, ECO-driven closure, Mentorship
Technologies
Cadence Innovus, Synopsys Fusion Compiler/ICC2, PrimeTime, Calibre
