Staff Engineer, RTL Design, AI Hardware
Core
Designing and optimizing micro-architectures for next-generation AI hardware silicon to unify software models, compilers, platforms, networking, and semiconductors.
Role type
Staff IC RTL Design Engineer (AI Hardware)
Builds
Custom AI platform silicon (ASICs/accelerators) for high-performance AI workloads
Domain
Semiconductor / AI Hardware / RISC-V
Deliverable
production ML models
Required skills
RTL design (Verilog/SystemVerilog), micro-architecture design, ASIC/accelerator delivery, PPA trade-offs, cross-functional technical leadership, root-cause analysis, design review and standards establishment
Preferred skills
silicon or post-silicon debug experience, mentoring engineers, establishing reusable design practices
Technologies
Verilog, SystemVerilog, RISC-V, synthesis tools, timing analysis tools
Responsibilities
Implement and optimize micro-architectures for AI hardware; lead complex PPA trade-offs across design, verification, and physical implementation; drive alignment across RTL, DV, performance, physical design, software, and architecture; identify and resolve novel failure modes and interface conflicts; provide technical direction and mentorship to engineers; represent the team in architecture and cross-functional reviews
Seniority
Staff, hands-on IC with technical direction and mentorship
