Silicon Design Engineer
Core
Front-End Silicon Design and Integration (FEINT) engineering for GFX Memory Controller IP, performing RTL synthesis, PPA analysis, and static verification to improve Quality of Result (QoR) for SoC products.
Role type
Senior IC silicon design engineer (FEINT)
Builds
High-performance System on Chip (SoC) products including GPU AI accelerators, graphics, and gaming controllers
Domain
Semiconductor / Hardware Design / SoC
Required skills
RTL synthesis, PPA analysis, ECO, static design rule checks, clock gating, Verilog, C/C++, scripting (Tcl, Ruby, Perl, Python), Unix/Linux, gate-level design concepts, VCS/Verdi
Preferred skills
RTL coding techniques for competitive PPA, RTL coding style for clean checks (LINT, CDC), physical design methodology
Technologies
Design Compiler/Fusion Compiler, Prime Time, Power Artist, PtPx, VCS, Verdi
Responsibilities
Develop RTL synthesis strategy and scripts for timing path and PPA analysis; Develop power redux strategy including hierarchical clock gating; Develop ECO strategy and perform LEC checks; Automate RTL static design rule checks and debug violations; Develop FEINT design and verification infrastructure
Seniority
Senior, hands-on IC
