Senior Physical Design Engineer
Core
Lead block-level and top-level implementation from floorplanning to GDSII stream-out for next-generation AI and PCIe Switch ASICs.
Role type
Senior Physical Design Engineer (ASIC)
Builds
Custom high-performance silicon solutions (AI, PCIe Switch)
Domain
Semiconductor / ASIC Physical Design
Required skills
Floorplanning, Placement, CTS, Routing, Timing Closure, Power Closure, Static Timing Analysis (STA), Signal Integrity (SI) Optimization, Power Grid Optimization, DRC/LVS, TCL, Python, Unix Shell Scripting
Preferred skills
High-speed clock network implementation (H-tree, mesh), Power-aware implementation flows (UPF/CPF, multi-voltage domains, clock/power gating)
Technologies
Cadence Innovus, Synopsys PrimeTime, Cadence Tempus, StarRC, QRC, RedHawk, Siemens Calibre
Responsibilities
Lead full-flow implementation from floorplanning to GDSII stream-out; Drive floorplanning, placement, CTS, routing, and timing/power optimization on advanced nodes (5nm, 3nm, 2nm); Perform multi-corner multi-mode (MCMM) static timing analysis (STA), signal integrity (SI) optimization, and power grid optimization for signoff.
Seniority
Senior, hands-on IC
