ASIC Physical Design Engineer - New College Grad 2027
Core
ASIC Physical Design Engineer responsible for digital chip implementation from RTL frozen to tape out, focusing on synthesis, timing closure, and flow automation.
Role type
ASIC Physical Design Engineer (New College Grad)
Builds
High-performance digital chips for AI, gaming, and accelerated computing
Domain
Semiconductor / ASIC Design
Deliverable
production ML models
Required skills
RTL design, Synthesis, Formal Verification, Timing closure, EDA tools (Synopsys/Cadence), Python/TCL scripting
Preferred skills
Chip partitioning, Floorplanning, Flow automation, Methodology development
Responsibilities
Chip integration and netlist generation, Synthesis, RTL/netlist quality check, Formal Verification, Constraints creation and validation, Timing closure/sign-off, Cross-team collaboration for partitioning and floorplan, Function eco creation, Flow automation development
Seniority
Entry-level, New College Grad
