ASIC Physical Design Engineer
Core
Full RTL-to-GDSII implementation flow for advanced semiconductor nodes, optimizing floor planning, timing, and power integrity for high-performance networking chips.
Role type
Senior IC ASIC Physical Design Engineer
Builds
High-performance networking chips (Switching, Routing, Wireless)
Domain
Semiconductor / Hardware / Networking
Required skills
RTL-to-GDSII flow, hierarchical floorplanning, place and route, static timing analysis (STA), power integrity, equivalence checks, clock tree synthesis (CTS), timing ECO implementation, EDA tools (Innovus, Tempus/Primetime, Redhawk/Voltus, Calibre), advanced process nodes (7nm/5nm/3nm)
Preferred skills
Python/TCL/Perl programming, timing closure, physical convergence, multi-mode/multi-corner scenarios
Technologies
Innovus, Tempus, Primetime, Redhawk, Voltus, Calibre, 7nm, 5nm, 3nm
Responsibilities
Drive RTL-to-GDSII implementation including hierarchical floorplanning, place and route, and static timing analysis; Analyze existing tool flows to identify efficiency gaps and implement enhancements; Collaborate with RTL, DFT, and EDA vendor teams; Guide clock tree synthesis strategies; Execute STA setup, convergence, and sign-off processes; Complete Timing ECO implementation using Tweaker/Primetime-based flows.
Seniority
Senior, hands-on IC
