Lead STA Engineer
Core
Lead Static Timing Analysis (STA) and timing closure for block- and full-chip designs to achieve Right-First-Time silicon.
Role type
Senior IC STA Engineer (Silicon Design)
Builds
Production silicon chips
Domain
Semiconductor / VLSI Design
Required skills
Static Timing Analysis (STA), timing closure, setup/hold analysis, OCV/AOCV/POCV, MMMC concepts, clock tree analysis, SDC creation, ECO implementation, timing constraints, scripting (Tcl/Perl/Python), low-power timing (UPF/CPF), signal integrity (SI) analysis, IR-drop analysis, variation-aware signoff
Preferred skills
Advanced technology nodes expertise, automation and flow development
Technologies
Synopsys PrimeTime, Cadence Tempus, Tcl, Perl, Python, UPF, CPF, SDC
Responsibilities
Perform full-chip and block-level STA across all modes and corners; Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations; Develop and maintain timing constraints including SDC creation and validation; Drive timing closure through ECO implementation and timing optimization; Analyze timing impact due to process, voltage, and temperature variations; Support timing signoff for pre-layout and post-layout stages; Generate timing reports and communicate closure status to project stakeholders.
Seniority
Senior, hands-on IC
