SoC Physical Design Engineer
Core
Own the physical design cycle for large-scale SoCs, including netlist to GDS implementation and verification.
Role type
Senior IC physical design engineer (SoC)
Builds
SoC chips for consumer electronics
Domain
Semiconductor / VLSI
Required skills
Block-level PnR, floor-planning, clock planning, power planning, static timing closure, physical verification, electrical/power analysis (EM/IR-Drop/Xtalk/noise), place & route tools (Synopsys/Cadence), scripting (TCL/Python/Perl/Shell)
Preferred skills
Verilog
Technologies
Synopsys, Cadence, TCL, Python, Perl, Shell
Responsibilities
Perform block-level PnR and floor-planning; Execute clock and power planning and distribution; Conduct static timing closure using commercial tools; Perform physical verification; Analyze electrical and power issues (EM, IR-Drop, Xtalk, noise).