Lead STA / Timing analysis Design Engineer
Core
Develop complex multi-mode/multi-corner timing constraints for RTL and signoff, drive pre-route timing checks, and ensure full-chip timing closure.
Role type
Senior IC silicon design engineer (STA/Timing)
Builds
High-frequency sub-chips, subsystems, and full-chip implementations for AI, data centers, PCs, gaming, and embedded systems.
Domain
Semiconductor hardware design
Required skills
SDC constraint development, EDA timing tool proficiency (Synopsys Design Compiler/Primetime, Fishtail, GCA), Tcl scripting, timing signoff methodology, physical design flow understanding, ECO implementation, DFT mode requirements, OCV/AOCV/POCV analysis
Preferred skills
8+ years experience in flat/hierarchical flows, high-frequency block timing closure (>GHz), Spyglass experience, DFT integration
Technologies
Synopsys Design Compiler, Synopsys Primetime, Fishtail, GCA, Spyglass, DMSA, Tweaker, Tcl, Linux
Responsibilities
Develop timing constraints compatible with RTL and signoff; Ensure constraints quality using industry tools; Drive pre-route timing checks and QoR cleanup; Perform timing closure for sub-chips, subsystems, or full chip; Generate timing ECOs using DMSA/Tweaker; Ensure full-chip interface timing closure along with DRV closure
Seniority
Senior, hands-on IC
