Physical Design - Engineer
Core
Physical implementation of subsystems including floor-planning, place and route, CTS, formal verification, physical verification, PDN, timing closure, and power optimization for PPA critical cores.
Role type
Senior IC physical design engineer
Builds
High-frequency data-path intensive cores and subsystems
Domain
Semiconductor hardware engineering (SoC physical design)
Required skills
Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, Power optimization, Clocking architecture, Tcl/Perl Scripting, Synopsys ICC2, Cadence Innovus, PTSI/Tempus
Preferred skills
PPA trade-off decisions, Block level PnR convergence, Advanced STA concepts
Responsibilities
Collaborate with design, DFT, and PNR teams to resolve constraints validation, verification, STA, and physical design issues.
Seniority
Mid-Senior, hands-on IC
