Embedded Soft IP Intern
Core
Design, verify, and release RTL-based IPs into Quartus and develop embedded reference designs for FPGA devices.
Role type
Embedded Soft IP Intern
Builds
RTL-based IPs and embedded reference designs for Altera FPGA devices
Domain
Semiconductor / FPGA Design
Required skills
Digital logic design, Computer architecture, Scripting (Python, Perl, TCL), System Verilog, Verilog, VHDL, FPGA design flows
Responsibilities
Design and validate existing and new IPs, Write functional tests and debug regression failures, Execute design flows and regressions, Participate in design discussions and reviews
