Lead Physical Design Engineer
Core
Lead physical design implementation for complex SoC architectures on 5nm and advanced sub-5nm technology nodes, owning P&R flows, physical verification, and timing closure.
Role type
Senior IC physical design engineer (SoC backend)
Builds
High-quality silicon for complex SoC architectures
Domain
Semiconductor / Digital IC Design
Required skills
Physical design (floorplanning, partitioning, placement, CTS, routing, sign-off), EDA tools (Cadence, Synopsys, Siemens), Tcl/Perl scripting, timing closure, DRC/LVS
Preferred skills
Automation flow development, cross-site team leadership, methodology improvement
Technologies
Genus, Innovus, Quantus, Tempus, DC, Star-RCXT, PT, PrimeRail, Voltus, Redhawk
Responsibilities
Drive top-down/bottom-up physical design integration for complex SoC architectures; Execute full backend flow from floorplanning to sign-off; Lead and mentor a small physical design team; Build and scale automation flows; Own timing and functional ECOs.
Seniority
Senior, hands-on IC
