Physical Design Automation Engineer
Core
Develop and optimize RTL-to-GDS physical design automation flows using Cadence Innovus for Intel's latest process nodes.
Role type
Senior IC Physical Design Automation Engineer
Builds
Production-ready RTL-to-GDS flows for internal product designs and external foundry customers
Domain
Semiconductor / VLSI Physical Design
Required skills
Cadence Innovus, Tcl scripting, Floorplanning, Placement, Clock Tree Synthesis, Routing, Static Timing Analysis, DRC/LVS sign-off, Timing closure methodologies
Preferred skills
Synopsys Fusion Compiler, Intel process technology, Block-level integration, Silicon tape-out experience
Technologies
Cadence Innovus, Cadence Tempus, Tcl
Responsibilities
Lead development of RTL-to-GDS flows; Define physical design tools and methodologies; Develop Tcl-based automation; Evaluate and benchmark EDA tools; Enable STA tools for test chips; Collaborate with design teams and EDA vendors; Support process node bring-up
Seniority
Senior, hands-on IC
