Low Power Design Engineer
Core
Designing power management logic for complex wireless communication SoCs to ensure energy efficiency and meet product requirements.
Role type
Senior IC low power design engineer (wireless SoC)
Builds
Wireless System on Chip (SoC) power management features
Domain
Semiconductor / Wireless Silicon / ASIC Design
Required skills
Verilog, ASIC low power design techniques, CDC/RDC/STA/UPF knowledge, scripting (Shell/Perl/Python), SoC component knowledge (CPU/fabric/peripherals), power/clock/reset logic design, post-silicon debug
Preferred skills
SoC level power management logic experience, SOC top level integration, system architecture knowledge, post-silicon functional debug and power correlation
Technologies
Verilog, Shell, Perl, Python, CDC, RDC, STA, UPF
Responsibilities
Define SoC power management features, Implement power management logic, Verify power management logic with XF teams, Support power analysis and post-silicon correlation, Post silicon bring up and debug
Seniority
Senior, hands-on IC
