Senior Physical Design Engineer
Core
End-to-end physical implementation and signoff of digital blocks and SoCs, covering RTL-to-GDSII flow.
Role type
Senior IC physical design engineer
Builds
Digital blocks and System-on-Chip (SoC) implementations
Domain
Semiconductor / Digital IC Design
Required skills
Floor-planning, Clock Tree Synthesis (CTS), Routing, Equivalence checking, Timing closure, Physical verification, DRC/LVS analysis, IR/EM analysis, Synthesis constraints, Cadence tools, Synopsys tools
Preferred skills
None stated
Technologies
Cadence, Synopsys
Responsibilities
Execute RTL-to-GDSII implementation activities including floor-planning, CTS, routing, equivalence checking, timing closure, and physical verification; Use industry-standard physical design flows for implementation, optimization, and signoff; Analyze and resolve timing, power, IR/EM, DRC, and LVS issues; Provide informed feedback on implementation results to the design team.
Seniority
Senior, hands-on IC
