Low Power Design/Methodology Engineer
Core
Design adaptive power management controllers, on-chip sensor controllers, and digital power meters for high-performance, low-power wireless and automotive SoC chips.
Role type
Senior IC low power ASIC design engineer
Builds
Low power IP blocks (power management, sensor control, digital power meter) integrated into wireless and automotive SoCs
Domain
Semiconductor / ASIC Design / Low Power Design
Required skills
RTL design, simulation, synthesis, timing analysis, formal verification, low power methodologies (UPF, CLP), Python/Perl/Tcl scripting, circuit analysis, logic design
Preferred skills
AVS (adaptive voltage scaling), power-aware DV, high-speed clocking, ISO 26262 functional safety (FMEA/FMEDA), SoC architecture/micro-architecture, silicon debugging
Technologies
Verilog, System Verilog, UPF, CLP, Python, Perl, TCL, Make
Responsibilities
Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, and formal verification for IP blocks; Collaborate with circuit design teams to close IP block specifications; Work with verification and physical design teams to complete IP implementation; Support SoC integration of low power/power management IP; Create and enhance low power methodologies from RTL to GDS; Provide feedback for low-power chip and system architecture; Perform block and chip-level power analysis; Understand and create block-level power models
Seniority
Senior, hands-on IC
