Staff Silicon Design Engineer – Physical Design
Core
Staff Silicon Design Engineer responsible for physical design integration, timing closure, and signoff for next-gen processors and AI chips.
Role type
Staff Silicon Design Engineer (Physical Design)
Builds
Next-generation processors and AI chips
Domain
Semiconductor / Physical Design
Deliverable
production ML models
Required skills
Floorplanning, placement, CTS, routing, optimization, ECOs, STA, SDC debugging, physical verification, Tcl, Python, Perl, shell scripting, AI-assisted workflows
Preferred skills
Synopsys Fusion Compiler, Cadence Innovus/PrimeTime/Tempus/StarRC/Calibre, hierarchical design, low-power design, EM/IR, reusable flow development
Technologies
Fusion Compiler, Innovus, PrimeTime, Tempus, StarRC, Calibre, Tcl, Python, Perl, shell
Responsibilities
Own RTL/netlist-to-GDS implementation including floorplanning, power planning, placement, CTS, routing, optimization, ECOs and closure; Drive timing closure through STA, constraints (SDC) debugging, interface timing analysis and ECO development; Support hierarchical physical design and integration at block, subsystem and top level; Resolve challenges in timing, congestion, clocking, power, area, signal integrity and physical verification; Support signoff: STA, DRC/LVS, antenna, low-power checks and EM/IR; Build reusable automation in Tcl, Python, Perl or shell; Use AI coding assistants and agentic tools to speed up run analysis, debug, scripting and workflow automation, and share what works across the team.
Seniority
Staff, hands-on IC
