Wissenschaftliche:r Mitarbeiter:in (m/w/d), EG 13 TV-H
Core
Research and development of algorithms for hardware design automation, focusing on FPGA/ASIC optimization and neural network implementation.
Role type
Research Scientist (Hardware Design Automation)
Builds
Optimized hardware architectures for FPGAs and ASICs
Domain
Electronic Design Automation (EDA), Hardware Architecture, Neural Networks
Deliverable
production ML models
Required skills
Algorithm design, Digital system design, Combinatorial/discrete optimization, Programming (C/C++/Java/Python), FPGA/ASIC design, Neural network training and optimization
Preferred skills
Hardware description languages (VHDL/Verilog), High-Level Synthesis, LLMs for complex problem solving, SAT/ILP optimization software
Technologies
FPGAs, ASICs, VHDL, Verilog, Python, C/C++, Java, SAT solvers, ILP solvers
Responsibilities
Develop and optimize algorithms for hardware design automation, Participate in academic teaching and supervision, Prepare and submit research grant proposals, Support third-party funded projects
Seniority
Mid-level Researcher (EG 13 TV-H)
