Staff Logic Design Engineer
Core
Architect and implement high-performance digital logic for protocol capture, analysis, and emulation in FPGA-based systems.
Role type
Staff Logic Design Engineer
Builds
High-speed protocol analyzers for data centers, AI/ML, storage, and networking
Domain
Semiconductor test & measurement / High-speed serial data communications
Deliverable
production ML models | product features
Required skills
RTL design (Verilog/SystemVerilog), FPGA development (Xilinx Versal, Intel Agilex), protocol decoding (PCIe, USB, Ethernet), verification (SystemVerilog/UVM), timing closure, CDC design
Preferred skills
Packet capture logic, AXI interconnects, SERDES integration, Python/Tcl scripting, hardware/software co-design
Technologies
Xilinx Vivado, Intel Quartus, ModelSim, PCIe IP cores, DMA engines
Responsibilities
Develop synthesizable RTL for packet parsing and buffer management; Perform synthesis, P&R, and timing closure on high-end FPGAs; Build SystemVerilog/UVM testbenches for verification; Collaborate with cross-functional teams to validate protocol analyzer platforms; Create design specifications and participate in code reviews
Seniority
Staff, hands-on IC
