STA Engineer
Core
Setting up and executing Static Timing Analysis (STA) environments for multi-voltage domains to achieve timing closure and ensure quality handoffs for physical design.
Role type
Senior STA Engineer
Builds
Timing-closed digital IC designs
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Multi-voltage domain STA, pre-route timing checks, SDC issue resolution, PnR-STA correlation, block-level high-speed session generation, timing ECO generation
Preferred skills
Tweaker, PrimeClosure
Technologies
Tweaker, PrimeClosure
Responsibilities
Setup, execution, and timing closure of Multi Voltage domain STA environment; Drive pre-route timing checks and QoR clean up to eliminate SDC issues; Ensure timing correlation between PnR and STA; Generate block level HS session and use Top context from SoC for Block-SoC Interface timing closure; Generate timing ECO using Tweaker/PrimeClosure.
