Physical Design Engineer
Core
Own block-level implementation and verification, drive timing closure and PPA optimization for ASIC infrastructure focused on inference workloads.
Role type
Senior Physical Design Engineer (ASIC)
Builds
ASIC blocks and infrastructure for frontier AI inference systems
Domain
Semiconductor / Hardware / AI Infrastructure
Deliverable
production ML models
Required skills
Block-level physical design, timing closure, PPA optimization, advanced process nodes (5nm and below), EDA tool flows (RTL synthesis to GDSII), sign-off tools (PrimeTime, Tempus, Voltus), low power design (UPF), formal verification, floorplanning, placement, CTS, routing, IR drop, EM/antenna analysis
Preferred skills
Python scripting, modern ML/LLM model architecture familiarity, AI tools for programming
Technologies
Cadence Innovus, Genus, Synopsys ICC2, Fusion Compiler, PrimeTime, Tempus, Voltus
Responsibilities
Run PD flows to close blocks and support ASIC infrastructure, automate PD flows and improve CAD infrastructure, collaborate with RTL designers to improve PPA, drive dashboards for project convergence, optimize tool flows with EDA vendors, supervise outsourcing of physical design
Seniority
Senior, hands-on IC