RTL Design Engineer
Core
Develop and implement design verification strategies for AI chips (ASICs) focused on inference workloads, ensuring correct and efficient operation of high-speed digital logic blocks.
Role type
Senior RTL Design Engineer (ASIC/Verification)
Builds
AI inference chips (ASICs) for frontier intelligence systems
Domain
Semiconductor hardware design / AI Infrastructure
Deliverable
production ML models
Required skills
RTL development, high-speed digital logic, RTL synthesis tools, verification methodologies, test bench creation
Preferred skills
PCIe/Ethernet/HBM technologies, ML/LLM model architectures, numerical representations, Python scripting
Technologies
Standard RTL design and synthesis tools
Responsibilities
Implement blocks for floating point math operators; Provide feedback to uArch team regarding timing and area constraints
Seniority
Senior, hands-on IC
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