Physical Design Engineer - SOC
Core
Physical design and timing closure for complex System-on-Chip (SOC) top-level implementations in mobile application processors, modem sub-systems, and connectivity chips.
Role type
Senior Physical Design Engineer (SOC)
Builds
Next-generation SOCs for mobile and connectivity applications
Domain
Semiconductor / VLSI / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Synthesis, Place and Route, Static Timing Analysis (STA), timing closure, floor planning, partition shaping, pin placement, channel planning, high-speed signal planning, clock planning, feed-through planning, PPA optimization, scripting (Perl/Tcl), LVS/DRC debugging, hierarchical design, deep sub-micron design knowledge (8nm/5nm), mixed-signal block integration, ESD strategies, multi-voltage/clock domain management
Preferred skills
Top-level floor planning expertise, experience with large SOC designs (>20M gates), frequencies >1GHz, recent successful SOC tape-outs
Technologies
ICC, DC, PT, VSLP, Redhawk, Calibre, Formality
Responsibilities
Perform complex SOC top physical implementation including synthesis, place and route, and STA; execute timing closure for complex blocks and full-chip designs; optimize PPA trade-offs; manage floor planning, pin placement, and channel planning; debug LVS/DRC issues at chip/block level; handle deep sub-micron design issues and mixed-signal integration
Seniority
Senior, hands-on IC
