Sr. Staff Digital DE
Core
Leads end-to-end design and development of digital and mixed-signal ICs for power management, signal management, and mixed-signal functions.
Role type
Senior/Staff Digital Design Engineer (ASIC)
Builds
Power management ICs, switching regulators, sensors, motor control, display drivers, audio amplifiers for portable and non-portable markets.
Domain
Semiconductor / Integrated Power Semiconductors
Deliverable
production ML models | product features
Required skills
Digital ASIC design, RTL Verilog/System Verilog, UVM/System Verilog verification, Backend flow (Synthesis, P&R, DFT, Power, LEC, STA), IP definition and integration, Post-Silicon validation support
Preferred skills
Automotive standards, Embedded designs/firmware, Power management applications, I2C/I3C/SPI/USB/PMBUS protocols, FPGA design, ARM designs, Scripting (TCL, Python, C/C++)
Responsibilities
Define digital architecture and documentation, RTL design and debugging, Verification metrics analysis, IP development and verification, Synthesis constraints and analysis, LEC constraints and debugging, P&R support, DFT implementation, ATPG generation, Gate-level verification, Power simulations, Timing analysis and sign-off, AMS verification support
Seniority
Senior/Staff, hands-on IC design
