Semiconductor Digital Architect, Texas Institute for Electronics
Core
Develop next-generation digital subsystems and compute fabrics for 2.5D/3D microsystems, enabling scalable, high-bandwidth integration across AI, HPC, and wireless acceleration platforms.
Role type
Senior IC semiconductor digital architect (2.5D/3D integration)
Builds
Next-gen digital subsystems, compute fabrics, and reference designs for AI/HPC/wireless platforms
Domain
Semiconductor design, 3D heterogeneous integration, chiplet architectures
Deliverable
production ML models | product features
Required skills
Digital/system architecture for SoC/FPGA/ASIC, dataflow architectures, memory hierarchies, interconnects, RTL design/verification (SystemVerilog/VHDL), hardware-software co-design, FPGA prototyping, performance modeling, architectural trade-off analysis
Preferred skills
PhD in Electrical/Computer Engineering, heterogeneous compute integration, multi-die packaging (2.5D/3D, hybrid bonding), AI/ML or 5G/6G hardware acceleration, interconnect standards (BoW, UCIe, CXL, NVLink, UALink)
Technologies
SystemVerilog, VHDL, SystemC, C++, Python, UALink, NVLink Fusion, UltraEthernet, CXL 3.x
Responsibilities
Architect digital subsystems and compute fabrics for 2.5D/3D microsystems; Define and optimize architecture specifications, dataflows, and interconnect topologies; Collaborate with EDA, packaging, and system modeling teams; Lead system-level modeling and design-space exploration; Engage with industry partners and standards bodies; Mentor internal design teams on RTL methodologies and IP integration; Translate architectural innovations into roadmaps and reference designs
Seniority
Senior, hands-on IC with mentorship responsibilities
