Sr Principal Design Engineer
Core
Design, implement, and verify RTL for PCIe controllers and related subsystems, ensuring protocol compliance and performance targets.
Role type
Senior IC RTL Design Engineer (PCIe Protocol)
Builds
PCIe Controller IP blocks and subsystems
Domain
Semiconductor / Hardware Design / PCIe Protocol
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design (Verilog/SystemVerilog), PCIe protocol stack (Gen4/Gen5/Gen6), AXI & PXC interfaces, DMA engines, MSI interrupt handling, CDC design principles, asynchronous FIFO implementation, synthesis, linting, static timing analysis, formal verification, assertion-based design, simulation tools, waveform debugging
Preferred skills
null
Technologies
Verilog, SystemVerilog, LINT, CDC tools, Synthesis tools, Simulation tools
Responsibilities
Architect and implement RTL for PCIe IP blocks, Collaborate with system architects to define micro-architecture and design specifications, Ensure design quality through LINT/CDC and Synthesis, Work closely with verification teams to develop testbenches and validate functionality, Participate in interoperability testing, Contribute to performance, power, and area optimization in advanced nodes, Interface with cross-functional teams including PHY, software, and validation
Seniority
Senior, hands-on IC
