Lead SOC RTL Design Engineer
Core
Lead RTL design and architecture for SoC subsystems and IP blocks, managing front-end design tasks and leading engineering teams.
Role type
Lead SOC RTL Design Engineer
Builds
SoC subsystems, IP blocks, and front-end design deliverables
Domain
Semiconductor, System LSI, SoC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SoC IP design, SoC Subsystem Designs, High Speed & Low Speed Protocol concepts, SPI/I2C/I3C/UART/PWM IP design, UCIe/Ethernet/UFS IP architecture, team leadership, AXI/AHB/APB interconnect protocols, Lint/CDC/UPF/VCLP/DFT/Power/Clock Flow, design timing closure, verification debug
Preferred skills
UCIe/Ethernet/UFS IP architecture
Technologies
Lint, CDC, UPF, VCLP, DFT, AXI, AHB, APB
Responsibilities
Architect block and sub-system at SOC level, manage and lead teams of 4-5 Engineers, manage SoC dependencies, planning and tracking of all front-end design related tasks, handle design timing closure and verification debug
Seniority
Senior, hands-on IC with management responsibilities
