Sr Design Engineering Architect
Core
Architecting and developing RTL for PCIe/CXL/IDE/UALink interface controller IP, including CPU, memory, IO, and cache subsystems.
Role type
Senior IC RTL Design Architect (Interface Controller IP)
Builds
PCIe/CXL/IDE/UALink IP solutions for Cadence customers
Domain
Semiconductor / VLSI / Interface Protocols
Deliverable
production ML models | product features
Required skills
RTL design and development, Verilog, System Verilog, UVM, CPU subsystem architecture, memory subsystem design, IO and cache subsystem design, PCIe/CXL/IDE protocol implementation
Preferred skills
IP development team experience, complex protocol implementation, scripting
Technologies
Verilog, System Verilog, UVM, PCIe, CXL, IDE, UALink
Responsibilities
Add new features to RTL, work with existing RTL, ensure clean customer configurations via verification regressions, support customers, ensure design compliance with LINT and CDC guidelines
Seniority
Senior, hands-on IC
