Lead Design Engineer
Core
Digital design implementation and PPA optimization of state-of-the-art Cadence IPs for advanced process nodes (7nm/5nm/3nm/2nm) using EDA tools.
Role type
Lead Design Engineer (Physical Design & EDA)
Builds
Performance and power-oriented best-in-class IP cores for advanced process nodes
Domain
Semiconductor / EDA / ASIC Design
Required skills
Synthesis, Physical Designing, Timing Analysis, Power Analysis, Formal Verification, Python, Perl, TCL, Unix shell, Digital logic design, Computer architecture
Preferred skills
Knowledge of complete ASIC Design Flow, Experience with Cadence digital design tools
Technologies
Genus, Innovus, Tempus, Voltus
Responsibilities
Implement digital design of Cadence IPs, Characterize and optimize PPA for IP cores, Develop and maintain EDA flows and scripts, Manage regression infrastructure for RTL/flow development, Participate in benchmarking PPAs for customer engagements
Seniority
Senior, hands-on IC
