Research Fellow/Senior Research Fellow (Front-end design (RTL) Scientist for Heterogeneous Systems)
Core
Research and development of secure, intelligent computing platforms using chiplet-based heterogeneous IC architectures.
Role type
Senior Research Fellow (IC Front-end Design & Security)
Builds
Chiplet-based architectures, NoC enhancements, and hardware security functions for future urban mobility applications.
Domain
Semiconductor / Heterogeneous Integration / Hardware Security
Deliverable
production ML models | product features | research
Required skills
IC front-end design, chiplet design, heterogeneous integration, cryptographic hardware engineering, system-level modeling and simulation, topology exploration, routing algorithms, protocol and flow control design, fault tolerance, hardware root-of-trust, cryptographic agility
Preferred skills
Experience with Xilinx Vivado, Cadence Virtuoso, Synopsys tools
Technologies
ARM, RISC-V, Xilinx Vivado, Cadence Virtuoso, Synopsys
Responsibilities
Design chiplet-oriented architectures and interposer strategies, develop fault-tolerant and robust system designs, prototype hardware security functions and NoC enhancements, contribute to long-term research strategy and white papers, publish in top-tier conferences and journals
Seniority
Senior, hands-on IC researcher
