SOC IP RTL Development Engineer
Core
Designing high-speed serial interface IP blocks for System LSI and Mobile SoCs.
Role type
Senior IC RTL Design Engineer (High-Speed SerDes)
Builds
USB, PCIe, Ethernet PHY, and other high-speed serial interface IP cores for Samsung SoCs.
Domain
Semiconductor / High-Speed SerDes / System LSI
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Front-end RTL design, IP-level architecture, High-Speed SerDes design, LINT/CDC/SYNTHESIS tools, Cross-functional collaboration, Mentoring
Preferred skills
Silicon debug, AFL/XPROP/DFT tools, Scripting (Perl/Python/Tcl/bash)
Technologies
LINT, CDC, SYNTHESIS, AFL, XPROP, DFT, Perl, Python, Tcl, bash
Responsibilities
Design front-end RTL and architecture for IP blocks, Support verification and coverage closure with SOC and DV teams, Mentor junior team members
Seniority
Senior, hands-on IC
