Principal Design Engineer
Core
Develop cycle-level performance models and architectural tradeoff analysis for next-generation DDR memory controller architectures to support complex SoC and workload requirements.
Role type
Principal Design Engineer (Performance Modeling)
Builds
Performance models and synthetic memory traffic traces for DDR memory controllers
Domain
Semiconductor hardware design, Computer Architecture, Memory Systems
Deliverable
production ML models | product features
Required skills
C++, SystemC, Transaction Level Modeling (TLM), Hardware modeling, Queuing Theory, Throughput/Latency tradeoff analysis
Preferred skills
RTL-Verilog/SV, UVM, Waveform analysis, Memory protocols (DDR4/5/LP4/5), Python (Pandas/Matplotlib), Performance benchmarks (SPEC/STREAM), QoS concepts
Technologies
SystemC, C++, Python, Pandas, Matplotlib, SPEC, STREAM
Responsibilities
Develop cycle-level performance models in SystemC or C++; Correlate performance models with RTL configurations; Analyze architectural trade-offs across scenarios; Develop synthetic memory traffic traces; Automate generation of performance metrics and statistics post simulation
Seniority
Senior, hands-on IC
