STA Lead Engineer
Core
Ensures timing closure for multi-mode, multi-voltage SoC and subsystem designs through full STA cycle management from constraints to GDS sign-off.
Role type
Senior STA Lead Engineer
Builds
Timing-optimized layouts for SoC and subsystem designs
Domain
Semiconductor Physical Design / Digital IC
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
STA setup and convergence, timing ECO management, logical equivalence checking, PVT validation, RTL-to-Netlist verification, floorplanning influence, CTS strategy influence
Preferred skills
Experience with multi-mode/multi-voltage designs, expertise in DMSA/PrimeClosure/tweaker flows
Technologies
PrimeTime, Tempus, DMSA, PrimeClosure, tweaker
Responsibilities
Perform STA setup, convergence, reviews, and signoff; Manage timing ECOs and conduct logical equivalence checks; Validate and debug timing across multiple PVT conditions; Collaborate with RTL, Synthesis, and Physical Design teams to influence floorplanning and CTS strategies
Seniority
Senior, hands-on IC
