Principal Design Engineer
Core
Architect and design state-of-the-art DDR memory controllers for Datacenter, Edge, Automotive, and AI applications.
Role type
Principal Design Engineer (Memory IP)
Builds
High-performance DDR memory controller IP for SoC integration
Domain
Semiconductor / Electronic Design Automation (EDA) / Memory
Deliverable
production ML models | product features
Required skills
Verilog RTL design, Metric Driven Verification (MDV), SoC architecture, Front-end design tools (LINT, Synthesis, CDC), Technical team leadership, High-speed circuit design, Low-power design
Preferred skills
AMBA protocols (CHI, AXI, AHB, APB), SystemVerilog, ISO-9001/ISO-26262 quality processes
Technologies
Verilog, SystemVerilog, LINT, Synthesis tools, CDC Analysis tools, Cadence Design Automation flow
Responsibilities
Architect solutions for latest DDR controller features, Design RTL in configurable/automated environments, Collaborate with Design Verification, Support, and PHY teams, Improve development processes through automation
Seniority
Principal, hands-on IC with leadership
