Senior RTL Design Engineer
Core
Senior RTL Design Engineer driving next-generation silicon architecture development, defining Physical Design methodologies, and leading sub-system/SoC integration for advanced ASICs.
Role type
Senior IC RTL Design Engineer (ASIC)
Builds
Complex chips and advanced silicon solutions for global networks
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features
Required skills
ASIC digital design, Verilog/System Verilog, front-end tools (simulation, linting, CDC, synthesis, formal verification), interface protocols (AMBA, JTAG), scripting (Python, Tcl, Make)
Preferred skills
Power optimization (UPF), DFT/MBIST
Technologies
Verilog, System Verilog, Python, Tcl, Make, AMBA, JTAG
Responsibilities
Take part in all aspects of digital design from micro-architecture to RTL design and qualification; Perform sub-system/SoC integration and verification; Review and enhance RTL codes; Improve flows and methodologies to streamline IP/SoC development; Collaborate with verification teams for complex debugs; Interact with physical design teams to optimize QoR
Seniority
Senior, hands-on IC
