<Data center>Digital IC Integration Technical Manager_Hsinchu/Taipei
Core
Leading SoC chip integration from RTL to gate level, ensuring timing closure, testability, and design methodology improvements.
Role type
Senior IC Integration Technical Manager
Builds
Production SoC chips
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | infrastructure
Required skills
RTL to gate level integration, timing closure, DFT structure planning, timing review and sign-off, floorplan planning, TOP IO and glue circuit design
Preferred skills
Design methodology improvement, integration flow optimization
Technologies
RTL, gate level, DFT, timing closure tools
Responsibilities
Perform SoC chip integration from RTL to gate level including timing closure and testability; Plan and design whole chip DFT structures; Conduct whole chip timing review and closure sign-off; Improve design methodology and integration flow; Plan Chip TOP IO and floorplan and design TOP glue circuits
