STA Lead Engineer
Core
Lead Static Timing Analysis (STA) engineer responsible for timing closure, constraint management, and mentoring teams in ASIC development.
Role type
Senior IC STA Lead Engineer
Builds
High-speed Chip and Subsystems
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static Timing Analysis (STA), Synthesis, Timing Closure, Low Power Design, Constraint Management, Perl/Tcl Scripting, Equivalence Checks, Floor-planning, CTS guidelines, Pre/post-layout timing analysis, Deep Sub Micron knowledge, Cross-talk noise/delay analysis, GCA, VCLP
Preferred skills
APR flows, IOs and IP constraints optimization, Automation of STA setup
Technologies
Verilog, Perl, Tcl
Responsibilities
Oversee and mentor a team of STA engineers for Chip and Subsystems; Develop constraints, run synthesis, perform low power, timing and equivalence checks and closure; Work closely with RTL designer, physical design, low power teams to optimize performance, area and power; Generate, review and validate design constraints to achieve timing closure of high speed design; Develop floor-planning and CTS guidelines for layout; Analyze pre-layout and post-layout timing, generate Timing and Power ECOs, and work closely with layout engineers to achieve critical high speed path timing closure; Perform in-house quality check before P&R and after P&R.
Seniority
Senior, hands-on IC with mentorship responsibilities
