Lead RTL Design Engineer
Core
Lead RTL design engineer developing the Cerebras Wafer Scale Engine (WSE) architecture for high-performance AI training and inference.
Role type
Lead front-end RTL design engineer
Builds
Next-generation Wafer Scale Engine (WSE) chips for AI workloads
Domain
Semiconductor hardware design / AI infrastructure
Deliverable
production ML models
Required skills
RTL design and integration, Micro-architecture definition, Synthesis, ASIC vendor management, Physical Design (PD) collaboration, Design Verification (DV) coordination, Silicon debugging, High-speed IO design, Networking stack expertise (TCP/IP, RDMA, Ethernet), Interface knowledge (PCIe, CPU, Serdes), Scripting (Python, TCL)
Preferred skills
FPGA development toolchain (Place and Route, Floor planning, Timing Analysis)
Technologies
Python, TCL, PCIe, Serdes, RDMA, Ethernet, TCP/IP
Responsibilities
Drive Functional Specification, Micro-architecture, RTL development, and Synthesis; Manage external ASIC vendors through product development; Collaborate with PD teams for PPA goals; Work with DV and DFT teams for functional and test coverage; Partner with software/system teams for performance optimization; Debug silicon-level functional, timing, and power issues during bring up.
Seniority
Senior, hands-on IC with management responsibilities
