STA methodology engineer
Core
Benchmark logic libraries across advanced technology nodes (40nm to 5nm) using synthesis and PNR flows to ensure robust STA methodologies for real-world chips and blocks.
Role type
Senior STA Methodology Engineer (IC)
Builds
Benchmarking frameworks for constraint validation and STA methodology evaluation
Domain
Semiconductor / Digital Logic Design / EDA
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
STA concepts, timing constraints, closure methodologies, DRCs, annotation, multivoltage flows, noise analysis, crosstalk analysis, synthesis flows, PNR flows
Preferred skills
Python scripting, AI/GenAI overview, STA flow automation development, industry-standard EDA tools
Technologies
Synthesis tools, PNR tools, EDA flows
Responsibilities
Benchmark logic libraries across multiple technology nodes, collaborate with cross-functional teams to validate timing constraints, develop and maintain benchmarking frameworks, perform comprehensive STA including timing analysis and noise/crosstalk checks, contribute to automation of STA flows
Seniority
Senior, hands-on IC
