Physical Design Engineer - Full Chip Implementation
Core
Full-chip physical design implementation for frontier AI inference clusters, encompassing floorplanning, P&R, clocking, timing analysis, and physical verification from synthesis to GDSII.
Role type
Senior Physical Design Engineer (Full Chip Implementation)
Builds
Frontier inference clusters (AI hardware)
Domain
Semiconductor / AI Infrastructure
Deliverable
production ML models
Required skills
Full-chip floorplanning, Multi-Mode Multi-Corner (MMMC) timing closure, hierarchical timing budgeting, physical verification (DRC/LVS/ERC), ECO closure, layout debugging in Innovus, advanced process node expertise (5nm and below), RTL-to-GDSII flow management
Preferred skills
Knowledge of modern ML/LLM architectures, Python scripting, startup experience
Technologies
Cadence Innovus, Genus, Synopsys Fusion Compiler, PrimeTime, Tempus, Pegasus, Calibre
Responsibilities
Own full-chip clocking across all PVT corners and modes; Manage MMMC timing closure at the top level; Drive functional and timing ECO closure for tapeout; Own end-to-end physical verification closure at block, sub-system, and full-chip levels; Debug complex PV violations and fix them directly in layout; Build a repeatable, tapeout-ready physical verification methodology
Seniority
Senior, hands-on IC
