Principal /Sr. Staff PD Implementation Expert
Core
Drive the complete RTL-to-GDSII physical design flow for next-generation, high-performance System-on-Chips (SoCs), focusing on aggressive Power, Performance, and Area (PPA) metrics.
Role type
Senior IC Physical Design Engineer (SoC Implementation)
Builds
High-performance SoCs for automotive, industrial, infrastructure, and IoT markets
Domain
Semiconductor / VLSI Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL-to-GDSII flow ownership, floor planning, synthesis, placement, Clock Tree Synthesis (CTS), routing, Static Timing Analysis (STA), Power Analysis, Signal Integrity Analysis, DRC/LVS/EMIR/LEC verification, Tcl/Python/Perl scripting
Preferred skills
Mentoring junior engineers, multi-voltage domain design, power gating (UPF), datapath optimization
Technologies
Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC, Calibre, Red Hawk
Responsibilities
Execute end-to-end physical design implementation including floor planning, synthesis, placement, CTS, and routing; Fine-tune designs to meet stringent PPA targets using advanced techniques; Resolve timing violations and signal integrity issues; Perform physical and formal verification (DRC, LVS, EMIR, LEC); Collaborate with RTL, DFT, and Signoff teams; Automate flows using scripting languages
Seniority
Senior, hands-on IC