ASIC Design Engineer - Hardware
Core
Define, develop, and deliver system-level IP and methodologies to measure performance on industry-leading GPUs and SOCs.
Role type
Senior IC ASIC Design Engineer (Hardware)
Builds
System-level IP, RTL designs, and performance monitoring flows for GPUs and SOCs
Domain
Semiconductor / Hardware Design / AI Acceleration
Deliverable
production ML models
Required skills
RTL design (Verilog), SystemVerilog verification, SOC architecture knowledge, design automation flows, scripting (Perl/Python), debugging (CDC, clocks, resets), cross-functional collaboration
Preferred skills
Object-oriented programming, system-level IP design (Clocks/DFT/Resets), silicon debug, physical design exposure
Technologies
Verilog, SystemVerilog, dc_shell, VCS, Debussy, GDB
Responsibilities
Define and automate flows for system-level IP delivery; Run and debug RTL checks (CDC, clocks, reset, latency); Design and implement RTL features (microarchitecture); Collaborate with architects, designers, and software engineers
Seniority
Mid-Senior, hands-on IC
