ASIC Physical Design and Timing Engineer - New College Grad 2026
Core
Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block, cluster, and full chip levels.
Role type
ASIC Physical Design and Timing Engineer
Builds
GPUs, CPUs, DPUs, and SoCs
Domain
Semiconductor / ASIC Design
Deliverable
production ML models
Required skills
Static Timing Analysis (STA), Timing convergence, EDA tools, Synthesis, Floor-planning, Placement, CTS, Routing, Power optimization
Preferred skills
Deep sub-micron process nodes, AI/LLM programming, Physical design optimization
Technologies
EDA tools
Responsibilities
Drive frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, and ECO implementation.
Seniority
Entry-level (New College Grad 2026)
