ASIC Physical Design and Timing Engineer - New College Grad 2026
Core
Drive physical design and timing analysis/closure for NVIDIA GPUs, CPUs, DPUs, and SoCs at block, cluster, and full chip levels.
Role type
ASIC Physical Design and Timing Engineer (New College Grad)
Builds
High-performance GPUs, CPUs, DPUs, and System-on-Chips (SoCs)
Domain
Semiconductor / ASIC Design / AI Acceleration
Deliverable
production ML models | product features
Required skills
Static Timing Analysis (STA), Timing convergence, Timing constraints management, EDA tools, Synthesis, Floor-planning, Placement, CTS, Routing, Power analysis
Preferred skills
Deep sub-micron process nodes, AI/LLM programming, Physical design optimization
Technologies
Industry standard EDA and timing convergence tools
Responsibilities
Drive frontend and backend implementation including synthesis, equivalence checking, and ECO implementation; Work in a cross-functional environment interacting with multiple teams
Seniority
Junior, Entry-level IC
